============================================================== Guild: wafer.space Community Channel: 📐 - Designing / 📦-cob / I think I'm more worried about tented After: 2026-07-31 11:59 p.m. Before: 2026-09-01 12:00 a.m. ============================================================== [2026-08-07 7:15 p.m.] essen__ [2026-08-07 7:15 p.m.] essen__ > I'm more worried about tented vias than fully open ones at least if they're thin enough for the epoxy to not just drip down; Not sure what you mean there, are you more worried about them being tented ? And if so, doesn't tented imply there is no dripping because the hole is closed ? Also, if you remember (I am still in the process of re-reading the entire thread), why where the via's tented only on one side in the first place ? [2026-08-07 7:25 p.m.] namibj If they're tented that means there could be air enclosed beneath that could vapor going up rather than down. [2026-08-07 7:26 p.m.] namibj The tented side didn't have an area of exposed ground plane [2026-08-07 7:26 p.m.] namibj (The chip was placed on and surrounded by a golden shiny ground plane that was exposed.) [2026-08-07 7:32 p.m.] essen__ Perfect, I was supposed to read it that way, we are aligned in our understanding 👌 [2026-08-07 8:08 p.m.] essen__ > For reliability IMO we should at least ask if they have a generic CTE-vaguely-matched loaded version available given that I don' think they'd require actually different processing beyond dosing the epoxy from the other dispenser. Also not sure what you mean here. I follow up to CTE (Coefficient of thermal expansion) and I have a vague understanding of how that would impact our bond finger design, but you lost me at "-vaguely-matched loaded version available given that I don' think they'd require actually different processing beyond dosing the epoxy from the other dispenser." [2026-08-07 8:09 p.m.] essen__ > Might be contingent on the tracability serial being included, though; in case they fall down after globbing and are all mixed up between projects somehow. We already have the qrcodes though. [2026-08-07 8:11 p.m.] essen__ Thermal management already looks pretty good (filled gnd plane), and apart from adding parts like heatsinks that would increase the BOM cost I don't think there is much to be done on that panel. [2026-08-07 8:14 p.m.] essen__ Thinking about it, I think the more effective approach for thermal management right now we be to add a fan to the pcb for chips for which that was a problem. 🤔 [2026-08-07 8:34 p.m.] namibj So normal glob tops are black [2026-08-07 8:34 p.m.] namibj The Run1 ones were clear [2026-08-07 8:35 p.m.] namibj They would not be visible under an opaque glob that is loaded with some substance that makes the composite (epoxy and whatever they load it with) behave closer to silicon than it would naturally due. [2026-08-07 8:37 p.m.] namibj How does the heat get away from the die proper? I mean like thermal vias as a concept but also keeping an eye on thermal expansion flexing and stressing the die attachment. [2026-08-07 8:52 p.m.] essen__ That is actually great news in terms of permeability. [2026-08-07 8:56 p.m.] essen__ Valid point there. Frankly I have no idea how I could even simulate that for evaluation, so I will be reading up on the literature on that one and making a best effort. Else, my mini test program, renaming it to my "torture test suite" should include thermal cycling, though that would be logistically much more challenging than what I had planned. [2026-08-07 8:58 p.m.] essen__ Do you recall why we want that in the first place ? [2026-08-07 8:59 p.m.] namibj probably the die attach wanted it and the gnd bond ring and then they felt like filling the space to the board-side pad ring with it as well and put the ground vias there [2026-08-07 9:06 p.m.] essen__ But why the through holes though ? [2026-08-07 9:07 p.m.] namibj idk {Reactions} 🫡 [2026-08-07 9:11 p.m.] essen__ Thanks for everything, I will be looking at adding the thermal vias for sure once I absorb about 300 more pages of literature on the topic to make sure and not trip over a rock 100s have already tipped over. [2026-08-07 9:25 p.m.] namibj well see I'm not sure that copper/holes is good for the balance of thermal resistance and CTE-match [2026-08-07 10:03 p.m.] essen__ Copper hole defiantly not a good idea. But apparently filled and copper caped vias are recommended. I will have to see who that impacts unit cost though. [2026-08-07 10:11 p.m.] namibj copper capped? You mean epoxy-filler-and-plated-over-vias? [2026-08-07 10:11 p.m.] namibj Those are available on the 6L process of JLC as default IIRC. [2026-08-07 10:44 p.m.] essen__ Apparently there is a thing such as copper filled to. But epoxy filled might still work. Do you recall if the PCB are made at JLC ? [2026-08-07 11:17 p.m.] namibj they have been made there so far; they do offer very competitve pricing for the needs so far. [2026-08-07 11:17 p.m.] namibj Copper filled is expensive-ish NRE wise for testing; might not matter much for series though. {Reactions} 👍 ============================================================== Exported 28 message(s) ==============================================================